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US10061272B2

Pipelined SAR ADC using comparator as a voltage-to-time converter with multi- …

University of Texas System

Abstract

A two-stage successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising is described. The SAR ADC includes a first stage comprising a SAR ADC; a voltage-to-time interface that translates a voltage-domain residue from the SAR ADC to a time-domain residue; and a second stage …

University
University of Texas System
Assignee
Board Of Regents, The University Of Texas System
Inventor
Yun Chiu
Priority date
June 12, 2016
Filing date
June 12, 2017
Grant date
August 28, 2018
Publication date
August 28, 2018
Language
en
Metadata fetched
August 29, 2026 00:25