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US11449658B2

Methods of generating integrated circuit (IC) layout synthetic patterns and …

University of Texas System

Abstract

A method can be executed by at least one processor of a computer to generate synthetic Integrated Circuit (IC) layout patterns, where the method can optionally include accessing attribute values of the IC layout pattern features generated using IC layout patterns from at least one at least one …

University
University of Texas System
Assignee
Board Of Regents, The University Of Texas System
Inventor
Gaurav Rajavendra Reddy
Priority date
November 12, 2019
Filing date
November 12, 2019
Grant date
September 20, 2022
Publication date
September 20, 2022
Language
en
Metadata fetched
August 29, 2026 00:30