← All patents

US20080122115A1

Three-dimensional Wafer Stacking with Vertical Interconnects

University of Texas System

Abstract

Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable polymer. The polymer is preferably lithographically patternable and photosensitive. Curing of the …

University
University of Texas System
Assignee
Board Of Regents, The University Of Texas System
Inventor
Dan O. Popa
Priority date
September 20, 2006
Filing date
September 20, 2007
Publication date
May 29, 2008
Language
en
Metadata fetched
August 29, 2026 00:18