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US20240187212A1

Method & apparatus for an ultra low power vlsi implementation of the 128-bit …

University of Texas System

Abstract

The present techniques may provide improved processing and functionality of performance of the 128-bit AES Algorithm, which may provide improved power consumption. For example, in an embodiment, an encryption and decryption apparatus may comprise memory storing a current state matrix of an …

University
University of Texas System
Assignee
The Board Of Regents Of The University Of Texas System
Inventor
Alekhya MUTHINENI
Priority date
April 12, 2019
Filing date
November 30, 2023
Publication date
June 06, 2024
Language
en
Metadata fetched
August 29, 2026 00:31