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US5912832A

Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded …

University of Texas System

Abstract

A method and apparatus for n-bit by n-bit multiplication is disclosed using paralleled 4-bit by 4-bit multipliers and cascaded adder structures. The cascaded adder structures may be used to produce non-pipelined, integer, n-bit by n-bit multipliers with higher throughput than systolic array …

University
University of Texas System
Assignee
Board Of Regents, The University Of Texas System
Inventor
Michael F. Flahie
Priority date
September 12, 1996
Filing date
September 12, 1996
Grant date
June 15, 1999
Publication date
June 15, 1999
Language
en
Metadata fetched
August 28, 2026 23:56